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rev. 1.0 8/14 copyright ? 2014 by silicon laboratories si871x/2x si871x/2x 5 k v led e mulator i nput , l ogic o utput i solators features applications safety regulatory approvals (pending) description the si871x/2x isolators are pin-compatible, single-channel, drop-in replacements for popular optocouplers with data rates up to 15 mbps. these devices isolate high-speed di gital signals and offer performance, reliability, and flexibility advantag es not available with optocoupler solutions. the si871x/2x series is based on silicon labs' proprietary cmos isolation technology for low-power and high-speed operation and are resistant to the wear-out effect s found in optocouplers that degrade performance with increasing temperature, forward current, and device age. as a result, the si871x/2x series offer longer service life and dramatically higher reliability compar ed to optocouplers. ordering options include logic output with and without output enable options. ? high speed: dc to 15 mbps ? 2.5 to 5.5 v logic output ? pin-compatible, drop-in upgrades for popular high-speed digital optocouplers ? performance and reliability advantages vs. optocouplers ?? resistant to temperature, age and forward current effects ?? 10x lower fit rate for longer service life ?? higher common-mode transient immunity: >50 kv/s typical ?? lower power and forward input diode current ? wide range of product options ?? inverting and non-inverting ?? disable output high, low or tri-state ? 1 channel diode emulator input ? propagation delay 30 ns ? up to 5000 v rms isolation ? 10 kv surge withstand capability ? aec-q100 qualified ? wide operating temperature range ?? C 40 to +125 c ? rohs-compliant packages ?? soic-8 (narrow body) ?? dip8 (gull-wing) ?? sdip6 (stretched so-6) ? industrial automation ? motor controls and drives ? isolated switch mode power supplies ? isolated data acquisition ? test and measurement equipment ? ul 1577 recognized ?? up to 5000 vrms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation) ? vde certification conformity ?? iec60747-5-2/vde0884-10 (basic/reinforced insulation) ? cqc certification approval ?? gb4943.1 patent pending pin assignments: see page 21 1 2 3 4 8 7 6 5 nc anode cathode nc vdd nc vo soic-8, dip8 industry standard pinout gnd uvlo e 1 3 6 5 4 anode cathode vdd vo gnd sdip6 industry standard pinout 2 nc uvlo e 1 2 3 4 8 7 6 5 nc anode cathode nc vdd en vo soic-8, dip8 with output enable industry standard pinout gnd e uvlo
si871x/2x 2 rev. 1.0 functional block diagram diode emulator i f a1 output stage (logic out) out vdd xmit gnd rec c1
si871x/2x rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. technical descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.1. device behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.2. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3. under voltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. input circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2. output circuit design and powe r supply connections . . . . . . . . . . . . . . . . . . . . . . . 18 5. pin descriptions (soic- 8, dip8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. pin descriptions (soic-8, dip8) with output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. pin descriptions (sdip6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9. package outline: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 10. land pattern: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11. package outline: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12. land pattern: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13. package outline: sdip6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 14. land pattern: sdip6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 15. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.1. top marking (8-pin narr ow body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.2. top marking explanati on (8-pin narrow body so ic) . . . . . . . . . . . . . . . . . . . . . . . 31 15.3. top marking (dip8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 15.4. top marking explana tion (dip8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 15.5. top marking (sdip6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15.6. top marking explana tion (sdip6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
si871x/2x 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions parameter symbol min typ max unit v dd supply voltage v dd 2.5 5.5 v input current i f(on) (see figure 1) 630ma operating temperature (ambient) t a C40 125 c table 2. electrical characteristics v dd = 5 v; gnd = 0 v; t a = C40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max unit dc parameters supply voltage v dd (v dd Cgnd) 2.5 5.5 v supply current i dd output high or low (v dd = 2.5 to 5.5 v) 1.5ma input current threshold i f(th) 3.6ma input current hysteresis i hys 0.34ma input forward voltage (off) v f(off) measured at anode with respect to cathode. 1v input forward voltage (on) v f(on) measured at anode with respect to cathode. 1.4 2.8 v input capacitance c i f=100khz, v f =0v, v f =2v 15 15 pf pf logic low output voltage v ol i ol =4ma 0.2 0.4 v logic high output voltage v oh i oh =C4ma v dd - 0.4 v dd - 0.2 v output impedance z o 50 ? enable high min v eh v dd - 0.4 v enable low max v el 0.4v enable high current draw i eh v dd =v eh =5v 0 a enable low current draw i el v dd =5v, v el = 0 v C30 0 a uvlo threshold + vdd uv+ see figure 8 on page 16. v dd rising 2.2 2.35 v uvlo threshold C vdd uvC see figure 8 on page 16. v dd falling 2 2.25 v uvlo lockout hysteresis vdd hys 50 100 mv
si871x/2x rev. 1.0 5 ac switching parameters (v dd =5v, c l =15pf) maximum data rate f data dc 15 m bps minimum pulse width mpw 66 ns propagation delay (low-to-high) t plh c l =15pf 5 50 ns propagation delay (high-to-low) t phl c l =15pf 5 50 ns pulse width distortion pwd | t plh C t phl | 2 5 n s propagation delay skew t psk(p-p) t psk(p-p) is the magnitude of the dif- ference in prop delays between dif- ferent units operating at same supply voltage, load, and ambient temp. 25ns rise time* t r c l =15pf 2.5 4 ns fall time* t f c l =15pf 2.5 4 ns device startup time t start 40s common mode transient immunity cmti output = low or high v cm =1500v (see figure 2) i f =6ma 35 50 kv/s *note: guaranteed by design and/or characterization table 2. electrical characteristics (continued) v dd = 5 v; gnd = 0 v; t a = C40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max unit
si871x/2x 6 rev. 1.0 figure 1. diode emulator model and i-v curve 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 anode to cathode voltage [v] diode emulator input current [ma] 700 ? 2.2 v 10 ? anode cathode esd anode cathode e
si871x/2x rev. 1.0 7 figure 2. common mode transient immunity characterization circuit oscilloscope 5 v isolated supply vdd vo 5 v supply high voltage surge generator vcm surge output high voltage differential probe gnd cathode anode input signal switch input output isolated ground 267 ? si871x/2x
si871x/2x 8 rev. 1.0 table 3. regulatory information* csa the si871x/2x is certified under csa component accept ance notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 1000 v rms reinforced insulation work ing voltage; up to 1000 v rms basic insulation working voltage. 60601-1: up to 250 v rms reinforced insulation working voltage; up to 500 v rms basic insulation working voltage. vde the si871x/2x is certified according to iec60747 and vde0884. for more details, see file 5006301-4880-0001. 60747-5-2: up to 1414 v peak for basic insulation working voltage. vde0884-10: up to 1414 v peak for reinforced insula tion working voltage. ul the si871x/2x is certified under ul1577 component reco gnition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si871x/2x is certified under gb4943.1-2011 . for more details, see file v2012cqc001041. rated up to 1000 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. *note: regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "8.ordering guide" on page 22. table 4. insulation and safety-related specifications parameter symbol test condition value unit soic-8 dip8 sdip6 nominal air gap (clearance) l(io1) 4.7 min 7.2 min 9.6 min mm nominal external tracking (creepage) l(io2) 3.9 min 7.0 min 8.3 min mm minimum internal gap (internal clearance) 0.016 0.016 0.016 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 v erosion depth ed 0.031 0.031 0.057 mm resistance (input-output)* r io 10 12 10 12 10 12 ? capacitance (input-output)* c io f=1mhz 1 1 1 pf *note: to determine resistance and capacitance, the si871x/2x is co nverted into a 2-terminal device. pins 1C4 (1C3, sdip6) are shorted together to form the first terminal, and pins 5C8 (4C6, sdip6) are shorted together to form the second terminal. the parameters are then measured between these two terminals.
si871x/2x rev. 1.0 9 table 5. iec 60664-1 (vde 0884) ratings parameter test condition specification soic-8 dip8 sdip6 basic isolation group material group i i i installation classification rated mains voltages < 150 v rms i-iv i-iv i-iv rated mains voltages < 300 v rms i-iv i-iv i-iv rated mains voltages < 450 v rms i-iii i-iii i-iv rated mains voltages < 600 v rms i-iii i-iii i-iv rated mains voltages < 1000 v rms i-ii i-ii i-iii table 6. iec 60747-5-2 (vde 0884-10) insulation characteristics* parameter symbol test condition characteristic unit soic-8 dip8 sdip6 maximum working insulation voltage v iorm 630 891 1140 v peak input to output test voltage v pr method b1 (v iorm x 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1181 1671 2138 v peak transient overvoltage v iotm t = 60 sec 6000 6000 8000 v peak pollution degree (din vde 0110, table 1) 222 insulation resistance at t s , v io =500v r s >10 9 >10 9 >10 9 ? *note: this isolator is suitable for reinforced electrical isolation only within the safety limit dat a. maintenance of the safety data is ensured by protective circuits. the si871x /2x provides a climate classification of 40/125/21.
si871x/2x 10 rev. 1.0 table 7. iec safety limiting values parameter symbol test condition max unit soic-8 dip8 sdip6 case temperature t s 140 140 140 c input current i s ? ja = 110 c/w (soic-8), 110 c/w (dip8), 105 c/w (sdip6), v f =2.8v, t j = 140 c, t a =25c 370 370 390 ma output power p s 111w note: maximum value allowed in the event of a failure; also see the thermal derating curve in figures 3, 4,and 5.
si871x/2x rev. 1.0 11 figure 3. (soic-8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 and vde0884-10 figure 4. (dip8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 and vde0884-10 table 8. thermal characteristics parameter symbol typ unit soic-8 dip8 sdip6 ic junction-to-air thermal resistance ? ja 110 110 105 oc/w 400 600 800 1000 1200 ower r ps, input current r is ps (mw) is (ma) 0 200 0 20406080100120140 output po ts r case temperature (c) 400 600 800 1000 1200 ower r ps, input current r is ps (mw) is (ma) 0 200 0 20406080100120140 output po ts r case temperature (c)
si871x/2x 12 rev. 1.0 figure 5. (sdip6) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 and vde0884-10 400 600 800 1000 1200 ower r ps, input current r is ps (mw) is (m a) 0 200 0 20406080100120140 output po ts r case temperature (c)
si871x/2x rev. 1.0 13 table 9. absolute maximum ratings* parameter symbol min max unit storage temperature t stg C65 +150 c operating temperature t a C40 +125 c junction temperature t j +140c average forward input current i f(avg) 30ma peak transient input current (< 1 s pulse width, 300 pps) i ftr 1 a reverse input voltage v r 0.3 v supply voltage v dd C0.5 7 v output voltage v out C0.5 v dd +0.5 v enable voltage v eout C0.5 v dd +0.5 v output source or sink current i o 22ma input power dissipation p i 90mw output power dissipation p o 163mw total power dissipation p t 253mw lead solder temperature (10 s) 260 c hbm rating esd 3 kv machine model esd 250 v cdm 2kv maximum isolation voltage (1 s) soic-8 4500 v rms maximum isolation voltage (1 s) dip8 4500 v rms maximum isolation voltage (1 s) sdip6 6500 v rms *note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet.
si871x/2x 14 rev. 1.0 2. application information 2.1. theory of operation the si871x/2x are pin-compatible, single-channel, drop-in replacements for popular optocouplers with data rates up to 15 mbps. the operation of an si871x/2x channel is analo gous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple architecture provides a robust isolated data path and requires no special considerations or initializat ion at start-up. a simplified block diagram for the si871x/2x is shown in figure 6. figure 6. simplified channel diagram rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver led emulator ~50 ? gnd v dd
si871x/2x rev. 1.0 15 3. technical description 3.1. device behavior truth tables for the si871x/2x are summarized in table 10. table 10. si871x/2x truth table summary* input enable output si8715 (non-inverting) off n/a low on n/a high si8716 (inverting) off high high on high low xl o wh i g h si8717 (non-inverting) off high low on high high xl o wh i - z si8718 (inverting) off high high on high low xl o wh i - z si8719 (inverting) off n/a high on n/a low si8720 (inverting) off high high on high low xl o wl o w *note: this truth table assumes vdd is powered (vdd> uvlo). if vdd is below uvlo, see "3.3.under voltage lockout (uvlo)" on page 16 for more information. when vdd < uvlo, the output state is not guaranteed. in this condition, the output level is determined by external circuity connected to the output.
si871x/2x 16 rev. 1.0 3.2. device startup during startup-up, for the si8716, output v o is high until v dd rises above the uvlo+ threshold for a minimum time period of t start . following this, the output is low when the current flowing from anode to cathode is > i f(on) . device startup, normal operation, and shutdown behavior for the si8716 is shown in figure 7. note that figure 7 assumes that enable is asserted and that the outputs are operat ing in their normal operating condition (inverting for the si8716). see table 10 for more details on the enable function. figure 7. si8716 operating behavior (i f > i f(min) when v f > v f(min) ) 3.3. under voltage lockout (uvlo) the uvlo circuit unconditionally drives v o to its default state when v dd is below the lockout threshold. referring to figure 8, upon power up, the si871x/2x is maintained in uvlo until vdd rises above vdd uv+ . during power down, the si871x/2x enters uvlo when vdd falls below the uvlo threshol d plus hysteresis (i.e., vdd < vdd uv+ C vdd hys ). figure 8. si871x/2x uvlo response i f v o v dd t start t plh t phl i f(on) i hys uvlo+ voltage level determined by external pull-up supply t plh vdd hys uvlo- t start 1.7 v dduv+ (typ) output voltage (v o ) 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 supply voltage (v dd - gnd) (v)
si871x/2x rev. 1.0 17 4. applications the following sections detail the input and output circuits necessary for proper operation of the si871x/2x family. 4.1. input circuit design opto coupler manufacturers typically recommend the circ uits shown in figures 9 and 10. these circuits are specifically designed to improve op to-coupler input common-mode rejection and increase noise immunity. figure 9. si871x/2x input circuit figure 10. high cmr si871x/2x input circuit the optically-coupled circuit of figu re 9 turns the led on when the contro l input is high. however, internal capacitive coupling from the led to the power and ground conductors can momentarily force the led into its off state when the anode and cathode inputs are subjected to a high common-mode transient. the circuit shown in figure 10 addresses this issue by using a value of r1 suff iciently low to overdrive the led, ensuring it remains on during an input common-mode transient. q1 shorts the led off in the low output state, again increasing common- mode transient immunity. some opto coupler applications recommend reverse-biasing the led when the control input is off to prevent coupled noise from energizing the led. the si871x/2x input circuit requires less current and has twice the off-state noise margin compared to opto couplers. however, high cmr opto coupler designs that overdrive the led (see figure 10) may require increasing the value of r1 to limit input current i f to its maximum rating when using the si871x/2x. in addition, there is no benefit in driving the si 871x/2x input diode into reverse bias when in the off state. consequently, opto coupler circuits usi ng this technique should either leave the negative bias circuitry unpopulated or modify the circuitry (e.g., add a clamp diode or curren t limiting resistor) to ensure that the anode pin of the si871x/2x is no more than C0.3 v with resp ect to the cathode when reverse-biased. r1 1 2 3 4 si871x/2x vdd open drain or collector control input anode cathode n/c n/c r1 1 2 3 4 si871x/2x vdd control input anode cathode n/c n/c q1
si871x/2x 18 rev. 1.0 new designs should consider the input circuit configurat ions of figure 11, which are more efficient than those of figures 9 and 10. as shown, s1 and s2 represent any suitable switch, such as a bjt or mosfet, analog transmission gate, processor i/o, etc. also, note that th e si871x/2x input can be driven from the i/o port of any mcu or fpga capable of sourcing a minimum of 6 ma (see figure 11b). additionally, note that the si871x/2x propagation delay and output drive do not significantly change for values of i f between i f(min) and i f(max) . figure 11. si871x/2x other input circuit configurations 4.2. output circuit desi gn and power supply connections gnd can be biased at, above, or below ground as long as the voltage on v dd with respect to gnd is a maximum of 5.5 v. v dd decoupling capacitors should be placed as clos e to the package pins as possible. the optimum values for these capacitors depend on load current and t he distance between the chip and its power source. it is recommended that 0.1 and 1 f bypass capacitors be used to reduce high-frequency noise and maximize performance. opto replacement applications should limit their supply voltages to 5.5 v or less. si871x/2x 1 2 3 4 +5v control input s1 n/c anode cathode n/c si871x/2x a b r1 s2 4 n/c 3 cathode 2 mcu i/o port pin anode r1 1 n/c
si871x/2x rev. 1.0 19 5. pin descriptions (soic-8, dip8) figure 12. pin configuration table 11. pin descriptions (soic-8, dip8) pin name description 1 nc* no connect. 2 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 nc* no connect. 5 gnd ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 6v o output signal. 7 nc* no connect. 8v dd output-side power supply input referenced to gnd (5.5 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane. 1 2 3 4 8 7 6 5 nc anode cathode nc vdd nc vo soic-8, dip8 industry standard pinout gnd uvlo e
si871x/2x 20 rev. 1.0 6. pin descriptions (soic-8, dip8) with output enable figure 13. pin configuration table 12. pin descriptions (soic-8, dip8) with output enable pin name description 1 nc* no connect. 2 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 nc* no connect. 5 gnd ground reference for v dd . this terminal is typically connec ted to ground but may be tied to a negative or positive voltage. 6v o output signal. 7 en output enable. tied to v dd to enable output. 8v dd output-side power supply input referenced to gnd (5.5 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane. 1 2 3 4 8 7 6 5 nc anode cathode nc vdd en vo soic-8, dip8 with output enable industry standard pinout gnd e uvlo
si871x/2x rev. 1.0 21 7. pin descriptions (sdip6) figure 14. pin configuration table 13. pin descriptions (sdip6) pin name description 1 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 2 nc* no connect. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 gnd ground reference for v dd . this terminal is typically connec ted to ground but may be tied to a negative or positive voltage. 5v o output signal. 6v dd output-side power supply input referenced to gnd (5.5 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane. 1 3 6 5 4 anode cathode vdd vo gnd sdip6 industry standard pinout 2 nc uvlo e
si871x/2x 22 rev. 1.0 8. ordering guide table 14. si871x/2x ordering guide 1,2,3 ordering part number (opn) ordering options input/output configuration data rate cross reference insulation rating enable pin/ output state when active pkg type logic output (available in soic-8, dip8, and sdip6) si8715bc-a-is high cmti non-inverting output 15 mbps 3.75 kvrms no, n/a soic-8 si8716bc-a-is high cmti inverting output 15 mbps acpl-061l, hcpl-0600, hcpl-0601, hcpl-0611 3.75 kvrms yes, high soic-8 si8717bc-a-is high cmti non-inverting output 15 mbps 3.75 kvrms yes, hi-z soic-8 si8718bc-a-is high cmti inverting output 15 mbps acpl-c61l, acpl-w70l 3.75 kvrms yes, hi-z soic-8 si8719bc-a-is high cmti inverting output 15 mbps 3.75 kvrms no, n/a soic-8 si8720bc-a-is high cmti inverting output 15 mbps 3.75 kvrms yes, low soic-8 si8715bc-a-ip high cmti non-inverting output 15 mbps acpl-4800, hcpl-2202, hcpl-2212 3.75 kvrms no, n/a dip8/gw si8716bc-a-ip high cmti inverting output 15 mbps 6n137, hcpl-2601, hcpl-2611 3.75 kvrms yes, high dip8/gw si8717bc-a-ip high cmti non-inverting output 15 mbps 3.75 kvrms yes, hi-z dip8/gw si8718bc-a-ip high cmti inverting output 15 mbps 3.75 kvrms yes, hi-z dip8/gw si8719bc-a-ip high cmti inverting output 15 mbps 3.75 kvrms no, n/a dip8/gw si8720bc-a-ip high cmti inverting output 15 mbps 3.75 kvrms yes, low dip8/gw notes: 1. all packages are rohs-compliant with pea k solder reflow temperatures of 26 0 c according to the jedec industry standard classifications. 2. si and si are used interchangeably. 3. aec-q100 qualified.
si871x/2x rev. 1.0 23 SI8715BD-A-IS high cmti non-inverting output 15 mbps acpl-w21l, ps9303l2 5.0 kvrms no, n/a sdip6 si8719bd-a-is high cmti inverting output 15 mbps acpl-w61l, acpl-w481, acpl-w70l, tlp2766f 5.0 kvrms no, n/a sdip6 table 14. si871x/2x ordering guide 1,2,3 (continued) ordering part number (opn) ordering options input/output configuration data rate cross reference insulation rating enable pin/ output state when active pkg type notes: 1. all packages are rohs-compliant with pea k solder reflow temperatures of 26 0 c according to the jedec industry standard classifications. 2. si and si are used interchangeably. 3. aec-q100 qualified.
si871x/2x 24 rev. 1.0 9. package outline: 8-pin narrow body soic figure 15 illustrates the package details for the si871x/2x in an 8-pin narrow-body soic package. table 15 lists the values for the dimensions shown in the illustration. figure 15. 8-pin narrow body soic package table 15. 8-pin narrow body soic package diagram dimensions symbol millimeters min max a1 . 3 51 . 7 5 a1 0.10 0.25 a2 1.40 ref 1.55 ref b0 . 3 30 . 5 1 c0 . 1 90 . 2 5 d4 . 8 05 . 0 0 e3 . 8 04 . 0 0 e 1.27 bsc h5 . 8 06 . 2 0 h0 . 2 50 . 5 0 l0 . 4 01 . 2 7 ? 0 ? 8 ? ?
si871x/2x rev. 1.0 25 10. land pattern: 8-pin narrow body soic figure 16 illustrates the reco mmended land pattern details for the si87 1x/2x in an 8-pin narrow-body soic. table 16 lists the values for the di mensions shown in the illustration. figure 16. 8-pin narrow body soic land pattern table 16. 8-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si871x/2x 26 rev. 1.0 11. package outline: dip8 figure 17 illustrates the package details for the si871x/2x in a dip8 package. table 17 lists the values for the dimensions shown in the illustration. figure 17. dip8 package table 17. dip8 package diagram dimensions dimension min max a 4.19 a1 0.55 0.75 a2 3.17 3.43 b 0.35 0.55 b2 1.14 1.78 b3 0.76 1.14 c 0.20 0.33 d 9.40 9.90 e 7.37 7.87 e1 6.10 6.60 e2 9.40 9.90 e 2.54 bsc. l 0.38 0.89 aaa 0.25 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si871x/2x rev. 1.0 27 12. land pattern: dip8 figure 18 illustrates the recommended land pattern details for the si871x/2x in a dip8 package. table 18 lists the values for the di mensions shown in the illustration. figure 18. dip8 land pattern table 18. dip8 land pattern dimensions* dimension min max c8 . 8 58 . 9 0 e2 . 5 4 b s c x0 . 6 00 . 6 5 y1 . 6 51 . 7 0 *note: this land pattern design is ba sed on the ipc-7351 specification. ?
si871x/2x 28 rev. 1.0 13. package outline: sdip6 figure 19 illustrates the package details for the si871x/2x in an sdip6 package. table 19 lists the values for the dimensions shown in the illustration. figure 19. sdip6 package table 19. sdip6 package diagram dimensions dimension min max a2 . 6 5 a1 0.10 0.30 a2 2.05 b0 . 3 10 . 5 1 c0 . 2 00 . 3 3 d 4.58 bsc e 11.50 bsc e1 7.50 bsc e 1.27 bsc l0 . 4 01 . 2 7 h0 . 2 50 . 7 5 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si871x/2x rev. 1.0 29 0 8 aaa 0.10 bbb 0.33 ccc 0.10 ddd 0.25 eee 0.10 fff 0.20 table 19. sdip6 package diagram dimensions (continued) dimension min max notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si871x/2x 30 rev. 1.0 14. land pattern: sdip6 figure 20 illustrates the reco mmended land pattern details for the si871x/2x in an sdip6 package. table 20 lists the values for the dimensions shown in the illustration. figure 20. sdip6 land pattern table 20. sdip6 land pattern dimensions* dimension min max c 10.45 10.50 e1 . 2 7 b s c x0 . 5 50 . 6 0 y2 . 0 02 . 0 5 *note: this land pattern design is ba sed on the ipc-7351 specification. ?
si871x/2x rev. 1.0 31 15. top markings 15.1. top marking (8-pin narrow body soic) 15.2. top marking explanatio n (8-pin narrow body soic) line 1 marking: customer part number si87 = base name of product series w = isolator product series (1 or 2) x = output configuration 5/9 = no enable 6 = enable, output high when active 7/8 = enable, output hi-z when active 0 = enable, output low when active s = performance grade: a = 15 mbps, 20 kv/ ? s minimum cmti b = 15 mbps, 35 kv/ ? s minimum cmti v = insulation rating c = 3.75 kv line 2 marking: rttttt = mfg code manufacturing code from the assembly purchase order form. r indicates revision. line 3 marking: circle = 43 mils diameter left-justified e4 pb-free symbol yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date.
si871x/2x 32 rev. 1.0 15.3. top marking (dip8) 15.4. top marking explanation (dip8) line 1 marking: customer part number si87 = base name of product series w = isolator product series (1 or 2) x = output configuration 5/9 = no enable 6 = enable, output high when active 7/8 = enable, output hi-z when active 0 = enable, output low when active s = performance grade: a = 15 mbps, 20 kv/ ? s minimum cmti b = 15 mbps, 35 kv/ ? s minimum cmti v = insulation rating c = 3.75 kv line 2 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from the assembly purchase order form. r indicates revision. line 3 marking: circle = 51 mils diameter center-justified e4 pb-free symbol country of origin (iso-code abbreviation) cc
si871x/2x rev. 1.0 33 15.5. top marking (sdip6) 15.6. top marking explanation (sdip6) line 1 marking: device 87 = base name of product series w = isolator product series (1 or 2) x = output configuration 5/9 = no enable 6 = enable, output high when active 7/8 = enable, output hi-z when active 0 = enable, output low when active s = performance grade: a = 15 mbps, 20 kv/ ? s minimum cmti b = 15 mbps, 35 kv/ ? s minimum cmti v = insulation rating c = 3.75 kv; d = 5.0 kv line 2 marking: rttttt = mfg code manufacturing code from the assembly purchase order form. r indicates revision. line 3 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. line 4 marking: country of origin (iso-code abbreviation) cc ?
si871x/2x 34 rev. 1.0 d ocument c hange l ist revision 0.9 to revision 1.0 ? updated table 2 on page 4. ? updated table 5 on page 9. ? updated table 6 on page 9. ? updated table 9 on page 13. ? updated figure 8 on page 16.
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